Comments on: Xilinx Works From The Edge Towards Datacenters With Versal FPGA Hybrids https://www.nextplatform.com/2022/02/03/xilinx-works-from-the-edge-towards-datacenters-with-versal-fpga-hybrids/ In-depth coverage of high-end computing at large enterprises, supercomputing centers, hyperscale data centers, and public clouds. Tue, 15 Feb 2022 02:24:37 +0000 hourly 1 https://wordpress.org/?v=6.7.1 By: Timothy Prickett Morgan https://www.nextplatform.com/2022/02/03/xilinx-works-from-the-edge-towards-datacenters-with-versal-fpga-hybrids/#comment-175390 Fri, 04 Feb 2022 20:06:20 +0000 https://www.nextplatform.com/?p=139955#comment-175390 In reply to Steven Casselman.

It will be interesting to see what they do, won’t it? There are all kinds of packaging options.

I can’t wait until we can mix and match components on lots of chiplets and make all kinds of SKUs. Imagine if we could design compute engines inside a node the same way we add and subtract features of a car, hit a button and say give me 200 or give me 10,000 or give me a million.

]]> By: Steven Casselman https://www.nextplatform.com/2022/02/03/xilinx-works-from-the-edge-towards-datacenters-with-versal-fpga-hybrids/#comment-175379 Fri, 04 Feb 2022 18:59:55 +0000 https://www.nextplatform.com/?p=139955#comment-175379 AMD needs to take one Zen module and some Xilinx fabric and put them in a package. Then you’d get rid of the need to go over PCIe to run a program. 10% of the code does 90% of the work but 90% of the code needs to be run at speed. You can’t have a big communication gap and expect to have the performance you’re looking for. If it runs in parallel put it in FPGA and the serial part that runs in software has to run at speed and the little Arms in FPGA SoCs don’t cut it.

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