Comments on: Details Emerge On China’s 64-Core ARM Chip

By: Mike Bruzzone

Mon, 24 Oct 2016 05:36:47 +0000

On observing the various associate network positioning and counter points, “silvermont core performance” (?) what many don’t get on their reversal “Atom Performance”, is that at the very least Phytium, look at the system, is a big beta validation consumer volume home server.

Igneous storage and network appliance servers may be too.

They’re both positioned for their commercial potentials certainly, but on elastic volumes they are consumer technologies in disguise and misrepresented by the competition including guarding Xeons

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By: BusyBee

Fri, 07 Oct 2016 15:28:41 +0000

For 64 cores within 100W, Phytium’s Mars sounds quite competitive. Intel’s Xeon Phi 7250 with 68 cores gets SPECint_rate2006 of 870 (from https://www.spec.org/cpu2006/results/res2016q2/cpu2006-20160613-41874.html ) and SPECfp_rate2006 of 870 (from https://www.spec.org/cpu2006/results/res2016q2/cpu2006-20160613-41873.html ). That 53% in integer performance gain and 81% in FP performance gain requires 215W, which is more than twice the power of Phytium’s Mars. However, per core CPU performance is rather poor. Even the clockspeed difference is telling, Intel’s Xeon Phi 7250 is 1.4GHz while Phytium’s Mars is 2GHz (43% clockspeed advantage). There could be compromises to the ARM core architecture to reduce power usage per core (which in turn reduces single thread performance), like in Cavium’s ThunderX case.

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By: Johny Doe

Wed, 07 Sep 2016 05:17:14 +0000

By: FirstToExaflopFTW

Sat, 03 Sep 2016 03:00:03 +0000

In reply to OranjeeGeneral.

Well the first part of 2017 is all about Zen but K12 is there locked away at the moment until AMD can get Zen out the door. I do not see AMD throwing away all of the Jim Keller managed K12 design team’s work, and AMD is currently using some Server SKUs based on some Arm Holdings’ reference design cores that will need to be updated to K12 once Zen is to market. If AMD has a custom ARMv8a ISA running micro-architecture that possesses SMT capabilities then AMD will have something very valuable to add to the custom ARM ISA running server market.

I do not see AMD trowing away its K12 investment, and more than likely K12 will be there in late 2017 or early 2018. Looking at IBM’s power8, and now Power9 designs, that are RISC ISA based, AMD’s K12 if it does in fact have SMT capabilities should be able to be eventually beefed up in a wider order superscalar fashion with SMT4, or SMT8, if K12 starts with SMT2 and maybe be able to take on some power based designs. IBM gets all that SMT(SMT4, or SMT8) processor thread hardware crammed onto its Power8/9 cores because the power8/9 RISC ISA is easier to implement in parallel decoder/execution fashion than any CISC designs, so the ARMv8A ISA and Scalable Vector Extensions (SVE) have potential to be improved upon if the K12 has indeed gotten the SMT capabilities that have been recently added to AMD’s new Zen x86 ISA designs.

Jim Keller is on video(YouTube) stating that there was plenty of sharing of the CPU core design ideas among Keller’s Zen and K12 design teams, so I take that to mean that maybe K12 will get SMT abilities, and the same caching systems and execution resources(FPU, Int units, Etc) as the Zen has, with the K12 design requiring less transistors to implement the ARMv8A and SVE extensions, than the Zen x86 CISC ISA designs. If anything may delay K12 it may be those SVE extensions 128-bit up to 2048-bit SVE FP math. Fujitsu is the first public licensee of the SVE extensions, with plans to include ARMv8-A cores with SVE in the Post-K RIKEN supercomputer in 2020. So the exaflop market starts with ARMv8A/SVE extensions rather than x86 or Power9 if that is any indication of the future for the custom ARMv8A ISA/SVE market’s potential.

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By: OranjeeGeneral

Fri, 02 Sep 2016 09:28:12 +0000

I think K12 is dead or definitely MIA it has become extremely quiet at AMD HQ about it

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