Comments on: Ventana Launches Veyron V2 RISC-V Into The Datacenter https://www.nextplatform.com/2023/11/07/ventana-launches-veyron-v2-risc-v-into-the-datacenter/ In-depth coverage of high-end computing at large enterprises, supercomputing centers, hyperscale data centers, and public clouds. Thu, 16 Nov 2023 19:45:50 +0000 hourly 1 https://wordpress.org/?v=6.7.1 By: Timothy Prickett Morgan https://www.nextplatform.com/2023/11/07/ventana-launches-veyron-v2-risc-v-into-the-datacenter/#comment-216225 Mon, 13 Nov 2023 14:09:39 +0000 https://www.nextplatform.com/?p=143203#comment-216225 In reply to Slim Jim.

Oooooooh. Interesting!

]]> By: Slim Jim https://www.nextplatform.com/2023/11/07/ventana-launches-veyron-v2-risc-v-into-the-datacenter/#comment-216165 Sat, 11 Nov 2023 22:36:47 +0000 https://www.nextplatform.com/?p=143203#comment-216165 In reply to Slim Albert.

The paper for that SC23 presentation is available in open access ( https://arxiv.org/abs/2309.00381 ). Figures 4 and 6 compare the 64-core Sophon SG2042 (64x XuanTie C920 RISC-V cores with 128-bit vectors) to 4-core Sandybridge, 18-core Broadwell, 28-core Icelake, and 64-core Rome, in single-core and multi-threaded modes, respectively. It makes fine reading for a cloudy weekend!

]]> By: Slim Albert https://www.nextplatform.com/2023/11/07/ventana-launches-veyron-v2-risc-v-into-the-datacenter/#comment-216134 Sat, 11 Nov 2023 03:36:02 +0000 https://www.nextplatform.com/?p=143203#comment-216134 In reply to HuMo.

Ah-ah-ah! Quite funny … I quite agree with your comment to TNP’s 05/18/23 piece on Meta’s Training and Inference Accelerator (MTIA) for DLRM, that has 64x(1-scalar + 1-vector) RISC-V cores on a PCIe board, with a huge fan ( https://www.nextplatform.com/2023/05/18/meta-platforms-crafts-homegrown-ai-inference-chip-ai-training-next/ )!

I just found that there’ll be some RISC-V HPC benchmark at SC23 Denver this Monday (Nov. 13), but the Author Abstract states “the x86 […] CPUs […] outperform the SG2042 by between four and eight times” ( https://sc23.conference-program.com/presentation/?id=ws_risc111&sess=sess455 ).

]]> By: Will https://www.nextplatform.com/2023/11/07/ventana-launches-veyron-v2-risc-v-into-the-datacenter/#comment-216132 Sat, 11 Nov 2023 01:48:54 +0000 https://www.nextplatform.com/?p=143203#comment-216132 In reply to Slim Jim.

Fetch width is 16 bytes, so 8-wide decode only for 16-bit instructions, and 4-wide for 32-bit instructions. Rename is just 4 wide…

The cache is per core. So total 1.6MB cache plus 4MB L3, or 5.6MB per core. That’s even more cache than Genoa (5MB total cache per core). Graviton 3 has just 1.6MB per core.

However the real kicker is that in order to beat Genoa, Veyron V2 needs twice the number of cores and cache (and thus die size). The large die size and relatively low per-core performance makes it uncompetitive for cloud uses.

]]> By: Timothy Prickett Morgan https://www.nextplatform.com/2023/11/07/ventana-launches-veyron-v2-risc-v-into-the-datacenter/#comment-216118 Fri, 10 Nov 2023 14:56:12 +0000 https://www.nextplatform.com/?p=143203#comment-216118 In reply to DSavic.

Having ported to Arm and Power, it is that much easier to port the Linux stack to RISC-V — so everyone tells me.

]]> By: DSavic https://www.nextplatform.com/2023/11/07/ventana-launches-veyron-v2-risc-v-into-the-datacenter/#comment-216113 Fri, 10 Nov 2023 13:00:26 +0000 https://www.nextplatform.com/?p=143203#comment-216113 Performance aside, what about RISC-V Software Ecosystem? We’ve seen many good ARM-based designs in the past, but it took 10 years to (seriously) enter DC …and the struggle is not completely over yet…?

]]> By: HuMo https://www.nextplatform.com/2023/11/07/ventana-launches-veyron-v2-risc-v-into-the-datacenter/#comment-216102 Fri, 10 Nov 2023 05:41:34 +0000 https://www.nextplatform.com/?p=143203#comment-216102 Seeing as this is the very first RISC-V article in many years that I see where not a single emotional enthusiasmatic proponent of the arch has commented with stilted blind enthusiasm, I think it can be unequivocally and conclusively determined that this arch is now finally completely and utterly dead, buried, and gone! Shalom, and RIP RISC-V! Folks of good computational faith should now get serious and start working on RISV-VI, or RISC-VJ (James Brown RISC machine!), the 2W3R arch that can actually perform well on dynamic language workloads (and graphs, and everything that matters really!)! As Cerebras’ Feldam almost said in his recent HPCWire interview: It’s high time to be “tossing your salad differently”! 8^p

]]> By: Slim Albert https://www.nextplatform.com/2023/11/07/ventana-launches-veyron-v2-risc-v-into-the-datacenter/#comment-216100 Fri, 10 Nov 2023 05:24:40 +0000 https://www.nextplatform.com/?p=143203#comment-216100 In reply to Slim Jim.

If it is indeed fifteen 32-bit instructions per clock, and 512 KB of L1$I per core, then I wonder if they can hit the apparent sweet spot of 2.5 mm^2 per core (at 4nm) that Neoverse V2 gets (at 7 nm) and Zen 4c has (at 5 nm)? Or maybe it is more of an “out-there” design, like Microsoft’s “chiplet cloud”, that is not realistically designed for tape-out ( https://www.nextplatform.com/2023/07/12/microsofts-chiplet-cloud-to-bring-the-cost-of-llms-way-down/ )?

]]> By: Slim Albert https://www.nextplatform.com/2023/11/07/ventana-launches-veyron-v2-risc-v-into-the-datacenter/#comment-216097 Fri, 10 Nov 2023 03:05:19 +0000 https://www.nextplatform.com/?p=143203#comment-216097 In reply to Hubert.

They could also focus (pivot) on interfacing with quantum computers, in pre- and post-processing roles, replacing FPGAs there. It’s not a very large market at present but it is the future (more so than dataflow I think). The Quantum Approximate Optimization Algorithm (QAOA), for example, could really help solve graph-oriented problems more efficiently than more conventional recursive bounded search tree algos that involve substantial backtracking by necessity (to tackle McCarthy’s non-determinism) (eg. https://www.nextplatform.com/2023/09/21/beyond-the-traveling-salesman-escape-routes-get-a-quantum-overhaul/ ).

]]> By: Hubert https://www.nextplatform.com/2023/11/07/ventana-launches-veyron-v2-risc-v-into-the-datacenter/#comment-216065 Thu, 09 Nov 2023 05:15:29 +0000 https://www.nextplatform.com/?p=143203#comment-216065 SiFive’s exit from the general purpose RISC-V CPU field, with layoff of its engineering team ( https://www.theregister.com/2023/10/25/riscv_champ_sifive_said_to/ ) just two months after the lacklustre Phoronix benchmark of its VisionFive 2 chip ( https://www.phoronix.com/review/visionfive2-riscv-benchmarks ), and two weeks before the RISC-V Summit North America 2023 (Nov.7-8), doesn’t really give confidence in that aspect of this architecture (as in Slim Albert’s first post above). Wrapping Ventana’s innovations around an OpenPOWER core, or focusing on RISC-V’s use within accelerators (or in IoT, or in hard drives, etc …) might be the winning pivot at this juncture.

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