Well… I was talking about a switch, not a server. And PCI-Express 5.0, not PCI-Express 4.0. Everyone will have PCI-Express 5.0 soon and then we can have some fun.

Correct! Thanks.

First sentence tense error.

“If the datacenter has been taken over…”

“has” –> “had”.

Hi Steven

Thanks for the comment. The idea I was trying to get out is that you need low latency interconnects for things like CXL to make remote memory look close like DRAM is in the CPU. Nvidia had to create NVLink to get this same effect with Power9 processors from IBM, for instance. (I realize CXL and NVLink are very different animals.) If the retimers take 60 nanoseconds and you need two of them to get distance between the CPU and the peripheral and the switch is taking on the order of 100 nanoseconds to 120 nanoseconds, then you are up to 220 nanoseconds to 240 nanoseconds for access from CPU across CXL to the device compared to, what?, maybe 90 nanoseconds for local CPU memory and 140 nanoseconds for remote CPU memory in a two-socket NUMA box (using monolithic Xeon SP processors). Average it out, and that CXL-attached memory in a GPU or FPGA or whatever is 2.5X times further away than the CPU memory inside the box with retimers that just adhere to the PCi-Exprtess 5.0 spec minimums. That may be a latency bridge too far for things to look seamless. With Microchip’s retimers plus its switch chip, you are on the order of 120 nanoseconds to 140 nanoseconds for that CXL memory access — almost the same as the CPU itself. Much smaller gap.